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Title:
ADDRESS SYSTEM OF MEMORY
Document Type and Number:
Japanese Patent JPS5570983
Kind Code:
A
Abstract:

PURPOSE: To enable to assign the address automatically in the insertion of memory plane, by deciding the interleaving mode automatically through the detection of the mounting state of the memory of the same memory.

CONSTITUTION: At the plane address lines 12AW12C, the data to decide the address of each memory plane is transferred from the lower rank memory plane 201 to the upper rank memory plane 200, and on the type lines 1414AW14C, the data representing the capacity of memory plane is transferred from the upper rank 200 to the lower rank 201, and on the type count lines 13AW13C, the data representing that how many sheets of the memory plane of the same capacity can be mounted in succession is transferred from the lower to the upper rank. On the interleaving mode lines 15AW15C, the mode deciding signal is transferred from the upper rank to the lower rank. The operational processing for signals on each line is made at the interleaving control circuit 8 in each plane, and the selection agreement signal 11 and the internal address 10 are fed to the memory plane 9.


Inventors:
BANDOU TADAAKI
FUKUNAGA YASUSHI
Application Number:
JP14235878A
Publication Date:
May 28, 1980
Filing Date:
November 20, 1978
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F12/06; G11C8/12; (IPC1-7): G11C8/00



 
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