Title:
半導体用接着組成物、それを用いた半導体装置および半導体装置の製造方法
Document Type and Number:
Japanese Patent JP3995022
Kind Code:
B2
Abstract:
[Problems] To provided an adhesive composition for semiconductor that permits handling without an occurrence of cracking or peeling off even when being flexed, that at the time of laminating, permits laminating on the electrode side of a semiconductor wafer provided with bump electrodes of which bump electrodes have a narrow pitch and a high pin proportion, that at the time of dicing, permits a high-speed cutting without any dicing dust contamination or defect, and that facilitates detection of alignment marks at the time of dicing and flip chip assembly. [Means for Solving Problems] There is provided an adhesive composition for semiconductor comprising an organic-solvent-soluble polyimide (a), an epoxy compound (b) and a hardening accelerator (c), wherein per 100 wt parts of the epoxy compound (b), there are contained 15 to 90 wt parts of the organic-solvent-soluble polyimide (a) and 0.1 to 10 wt parts of the hardening accelerator (c), wherein the epoxy compound (b) contains a compound being liquid at 25°C under 1.013×10 5 N/m 2 and a compound being solid at 25°C under 1.013×10 5 N/m 2 , and wherein a ratio of compound being liquid based on all the epoxy compounds is 20 wt% or more and 60 wt% or less.
Inventors:
Koichi Fujimaru
Toshio Nonaka
Toshio Nonaka
Application Number:
JP2007048834A
Publication Date:
October 24, 2007
Filing Date:
February 28, 2007
Export Citation:
Assignee:
TORAY INDUSTRIES,INC.
International Classes:
H01L21/60; B32B27/00; C08L63/00; C08L79/08; C09J7/02; C09J179/08; H01L21/52
Domestic Patent References:
| JP2004137411A | ||||
| JP2004292821A | ||||
| JP11220051A | ||||
| JP2005183855A | ||||
| JP2005332901A |