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Title:
AGC CIRCUIT
Document Type and Number:
Japanese Patent JP2002016459
Kind Code:
A
Abstract:

To provide an AGC circuit capable of enlarging the change quantity of a gain in respect to the variable quantity of an AGC voltage by preventing a source potential from being lowered even when the drain current of a dual gate type field effect transistor(FET) provided in the AGC circuit is changed.

A circuit part 3 for bias is connected to a source terminal S of an FET Q1. Between the source terminal S and a ground terminal, the serial circuit of resistors R4 and R5 is connected, the node of the resistors R4 and R5 is connected to the base of a transistor Q2, the emitter of the transistor Q2 is grounded and the collector is connected through a resistor R6 to a power source VDD. Besides, the power source VDD is successively connected through the collector and emitter of a transistor Q3 to the source terminal S and the collector and base of the transistor Q3 are respectively connected to both the terminals of the resistor R6.


Inventors:
KUROSAKI HIROSHI
Application Number:
JP2000197955A
Publication Date:
January 18, 2002
Filing Date:
June 30, 2000
Export Citation:
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Assignee:
KENWOOD CORP
International Classes:
H03G3/10; (IPC1-7): H03G3/10
Attorney, Agent or Firm:
Masahiro Fukuyama



 
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