Title:
ALIGNER AND EXPOSING METHOD
Document Type and Number:
Japanese Patent JP3251362
Kind Code:
B2
Abstract:
PURPOSE: To obtain an aligner for forming a circuit pattern on a wafer with no positional shift by imparting strain for offsetting the positional shift of circuit pattern to a wafer thereby correcting and eliminating run out and wafer process strain.
CONSTITUTION: Amount of warp is measured for a wafer 5 before it is loaded to a wafer loading stage 30 of an aligner. A displacement control signal generator 36a operates correcting/removing amount of run out component and wafer process strain component obtained from a laser interferometer and delivers control amounts for correction and removal to the wafer loading stage 30 through a wafer stage drive controller 39. After the amount of warp is measured, the wafer 5 is mounted flatly on the wafer loading stage 30 by vacuum suction and then deformed into a desired shape by a microdisplacement means 303 fixed to the rear of the stage. This constitution corrects/removes run out and wafer process strain thus providing a circuit pattern having no positional shift on the wafer 5.
Inventors:
Yoshihiko Ozaki
Kenji Marumoto
Makoto Tabata
Koji Naemura
Hitoshi Kametani
Masaki Yukimaru
Toyoki Kitayama
Kenji Marumoto
Makoto Tabata
Koji Naemura
Hitoshi Kametani
Masaki Yukimaru
Toyoki Kitayama
Application Number:
JP1785093A
Publication Date:
January 28, 2002
Filing Date:
January 11, 1993
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
G03F7/20; H01L21/027; (IPC1-7): H01L21/027; G03F7/20
Domestic Patent References:
| JP5917247A | ||||
| JP5969926A | ||||
| JP58219735A | ||||
| JP4293225A | ||||
| JP3185808A | ||||
| JP63260023A |
Attorney, Agent or Firm:
Hiroaki Tazawa (2 outside)
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