PURPOSE: To attain the optimum matching between stages and to improve the yield by using a connection terminal provided between stages to perform the matching control between stages.

CONSTITUTION: Connection terminals 12 and 13 are provided among stages of FETs 4 and 5. Then characteristic impedance lines 14 and 15 of 50Ω are used to secure connection between an input terminal 2 and the terminal 12 as well as an output terminal 3 and the terminal 13 respectively. Thus the impedances of the FETs 4 and 5 are measured when viewed from a position between stages. A pattern of a microstrip line is controlled in order to give the complex conjugate matching between said impedances of FETs 4 and 5. A chip capacitor is set after removing lines 14 and 15, and the microstrip line is connected. Therefore the perfect matching is attained between stages. In this way, the satisfactory actuation of the FET is ensured and also the yield is improved.