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Title:
ANALOG ADDITION-SUBTRACTION CIRCUIT
Document Type and Number:
Japanese Patent JPH11353407
Kind Code:
A
Abstract:

To enable a neuro amplifier of a single stage to perform both addition and subtraction by refreshing an inverter so as to set the output of the inverter at the reference voltage level and switching the input voltage levels in a state where plural levels of input voltage are applied to the input terminals.

A control signal ADD is fetched at a high level in a state where the addition and subtraction inputs are applied to the terminals 11 and 12. Thus, a switch SW is closed to eliminate the charge of a feedback capacitor Cf. Then a neuro amplifier 10 is refreshed and output voltage Aout is set at the reference voltage level. Under such conditions, the charge set based on the input voltage Ain1(+)... is accumulated in the parallel capacitors Ci1.... Then an input terminal 13 is connected to the terminal 12 when the signal ADD is set at a low level, and a current set based on the difference between the voltage Ain1(+)... and the input voltage Ain(-)... flows to the capacitors Ci1.... The amplifier 10 displaces the voltage Aout to set the potential of the terminal 13 at 0. Therefore, no refreshing action is required before an arithmetic operation.


Inventors:
IMAIZUMI ICHIRO
HIGUCHI HIROSHI
SHU NAGAAKI
Application Number:
JP15822398A
Publication Date:
December 24, 1999
Filing Date:
June 05, 1998
Export Citation:
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Assignee:
KOKUSAI ELECTRIC CO LTD
TAKATORI IKUEIKAI KK
International Classes:
G06G7/14; G06F15/18; G06N3/06; H03F3/70; H03H19/00; H03K17/22; (IPC1-7): G06G7/14; G06F15/18; H03F3/70; H03K17/22
Attorney, Agent or Firm:
Ryuka Akihiro



 
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