To execute highly accurate analog/analog multiplication by adopting a threshold value circuit for which practically minimum of one piece of nMOS or pMOS is a switch for suppressing the parasitic capacitance of inverter input.
A first threshold value circuit TH1 is provided with 2-input capacitive coupling composed by integrating the output of capacitance C4 connected to the output of a first timer T1 and the capacitance C5 for inputting a first input voltage X and the output of the 2-input capacitive coupling is inputted to a serial circuit for which the threshold value circuit N1 and an inverter 11 are successively and serially connected. Then, the threshold value circuit N1 is composed by connecting resistance to the drain of one piece of the nMOS or connecting the resistance to the drain of one piece of the pMOS and performs a threshold value processing to the voltage while minimizing the parasitic capacitance to the voltage at an output terminal. In such a manner, practically the minimum of one piece of the nMOS or the pMOS is adopted as the switch and the parasitic capacitance is made small.
WASHITANI MOTOO
KOTOBUKI KOKURIYOU
