To reduce the size of an analog-digital conversion device and to decrease the throughput needed to correct an error due to a mismatch between interleaves.
The analog-digital conversion device converts an analog input signal into a digital output signal. The analog-digital conversion device includes an analog-digital conversion unit 12, a pseudo-alias signal generation part 114, a gain control part 116, and an alias signal correction part 118. The analog-digital conversion unit 12 converts the analog input signal into a plurality of digital signals. The pseudo-alias signal generation part 114 generates a pseudo-alias signal simulating an alias signal component included in a composite signal composed of the plurality of digital signals. The gain control part 116 generates a gain control signal controlling the gain of the digital output signal using the pseudo-alias signal. The alias signal correction part 118 corrects the alias signal component using the gain control signal.
MATSUNO JUNYA
YAMAJI TAKAFUMI
FURUTA MASANORI
| JP2004328436A | 2004-11-18 | |||
| JP2009239847A | 2009-10-15 | |||
| JP2009159534A | 2009-07-16 |
Yasukazu Sato
Yasushi Kawasaki
Takeshi Sekine
Akaoka Akira
Daisuke Kimoto