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Title:
ANALOG INTEGRATION DEVICE AND CORRELATION DEVICE USING THE SAME
Document Type and Number:
Japanese Patent JPH11196066
Kind Code:
A
Abstract:

To provide an analog integration device with high arithmetic accuray, regardless of the small size and low power consumption and to provide a correlation device.

In an analog integration device 3 of a switched capacitor type, one terminal of an offset compensation capacitor C33 is connected to a non- inverting input terminal of an amplifier A31. A reference voltage Vref is applied to the non-inverting input terminal via a switch SW33 for a refresh period and the other terminal of the capacitor C33 is connected to an output terminal of the amplifier A31 via a switch SW34. Thus, charges in response to an offset voltage are stored in the capacitor C33. During the arithmetic operation, the switch SW33 is interrupted and the reference voltage Vref is applied to an output side terminal of the capacitor C33 via the switch SW34. As a result, an offset voltage is applied to the non-inverting input terminal, and a correlation device 1 calculates an accurate correlation value.


Inventors:
OSAKA MORIO
MIYAMA RIYUUJI
Application Number:
JP109198A
Publication Date:
July 21, 1999
Filing Date:
January 06, 1998
Export Citation:
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Assignee:
SHARP KK
International Classes:
G06G7/19; H03H19/00; H04B1/709; H04J13/00; (IPC1-7): H04J13/00; G06G7/19; H03H19/00
Attorney, Agent or Firm:
Kenzo Hara