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Patent Searching and Data


Title:
ANALOG MULTIPLICATION CIRCUIT
Document Type and Number:
Japanese Patent JP2001077633
Kind Code:
A
Abstract:

To remove a leak component without using the active filter of high performance and to eliminate frequency dependency from removal effect.

Four NMOS transistors M3 to M6 constituting a source follower circuit supply base band signals to the drains of the NMOS transistor M1 and the NMOS transistor M2, which constitute a transistor pair, supply signals obtained by inverting the base band signals to the source of the NMOS transistor M1 and the NMOS transistor M2, which form the transistor piar. A carrier signal is applied to the gate of one MOS transistor forming the transistor pair and a signal obtained by inverting the carrier signal is supplied to the gate of the other MOS transistor.


Inventors:
YOSHIDA SATOSHI
YOSHIDA YOSHIKAZU
Application Number:
JP25345499A
Publication Date:
March 23, 2001
Filing Date:
September 07, 1999
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
G06G7/163; H03D7/14; H04L27/04; H04M1/00; (IPC1-7): H03D7/14; H04L27/04; H04M1/00
Attorney, Agent or Firm:
Yukio Sato