Title:
ANALOG MULTIPLIER
Document Type and Number:
Japanese Patent JP3189710
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an analog multiplier extending an input range and an output range by operating by a low power source voltage.
SOLUTION: This multiplier applies voltage corresponding to a first input voltage to cross-connected first/second differential pairs Q1/Q2 and Q3/Q4 and drives the common emitter of the first/second differential pairs Q1/Q2 and Q3/Q4 respectively by a differential current corresponding to a second signal voltage to take out a differential current proportional to the multiplication of the first input voltage and a second input voltage from a cross connecting point. In this case, the differential output current of a fourth differential pair inputting the second signal voltage is folded at at least first/second current mirror circuits to respectively be supplied to the common emitter of the first/ second differential pairs Q1/Q2 and Q3/Q4.
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Inventors:
Takashi Muraoka
Application Number:
JP28915296A
Publication Date:
July 16, 2001
Filing Date:
October 11, 1996
Export Citation:
Assignee:
NEC
International Classes:
G06G7/163; H03D7/14; (IPC1-7): G06G7/163
Domestic Patent References:
| JP6139378A | ||||
| JP333989A | ||||
| JP56162176A | ||||
| JP375977A |
Attorney, Agent or Firm:
Asamichi Kato