To provide an analog multiplying circuit in which a MOS transistor is used, with a wide input dynamic range and to degrade no output waveform and frequency response characteristic.

Currents proportional to input signals X, Y flow in NMOSs 17 and 18, a voltage proportional to the sum of the input signals X and Y is outputted to a resistor 19 and is applied to the gate of a source-grounded NMOS 20. Thus, a current proportional to the square of the sum of the input signals X and Y flows in the NMOS 20. On the other hand, input signals, X and Y are applied to gates of source-grounded PMOSs 22 and 23 respectively, current proportional to the square of the input signals X, Y flows in the PMOSs 22, 23 respectively. Current proportional to (X+Y)2-(X2+Y2), namely, 2XY flows in a resistor 21 connected in parallel with the PMOSs 22 and 23 and an output voltage Z as a multiplication result is outputted to a node N1.