Title:
ANALOG MULTIPLYING CIRCUIT
Document Type and Number:
Japanese Patent JP2003016379
Kind Code:
A
Abstract:
To provide an analog multiplying circuit which can obtain a desired multiplication output of an input current with simple circuit constitution.
This circuit has at least a gate voltage control part 1 having a 1st operational amplifier 13 and a 1st MOSFET 14 operating in an MOS resistance area and an arithmetic part 3 having a 2nd operational amplifier 32, a 1st resistance 31, a current mirror circuit 34, and a 2nd MOSFET 33 operating in an MOS resistance area; and a 1st input current I1 is supplied to the 1st MOSFET 14 and a 2nd input current I2 is supplied to the 1st resistance 31 respectively to obtain the output current IOUT generated by multiplying I1 and I2 from a transistor 36 on the output side of a current mirror circuit 34.
More Like This:
Inventors:
KAWACHI SHUHEI
Application Number:
JP2001199317A
Publication Date:
January 17, 2003
Filing Date:
June 29, 2001
Export Citation:
Assignee:
A & CMOS COMM DEVICE INC
International Classes:
G06G7/16; H03F3/343; (IPC1-7): G06G7/16; H03F3/343
Attorney, Agent or Firm:
Sato Eto
Previous Patent: MULTIDIMENSIONAL MATRIX INPUT PICTURE GENERATING DEVICE
Next Patent: BAR CODE READER
Next Patent: BAR CODE READER