To provide an analog signal multiplying circuit suitable for MOS integrated circuit.

An analog signal multiplying circuit is provided with four MOS transistors 1a-1d whose sources are connected with each other. Two of differential inputs Vx+, Vx-, Vy+, and Vy- are differently combined and inputted through two capacitors 4 with the same capacity to each gate. Moreover, two of each drain are connected with one end of a load resistance 2a, and the residual drains are connected with one end of a load resistance 2b. Thus, output signals proportional to the product of two input signals inputted as differential inputs are outputted from the end parts of the load resistance 2a and 2b as differential outputs Vo+ and Vo-. Also, the both ends of each capacitor 4 is short-circuited by a switch 3, and the floating of each gate is compensated in a period in which the multiplication is not operated.