Title:
ANTENNA SWITCH CIRCUIT
Document Type and Number:
Japanese Patent JP3194310
Kind Code:
B2
Abstract:
PURPOSE: To provide an antenna switch circuit matching an input impedance of a reception system circuit and attenuating a signal to a proper level in the reception of a large level signal in a digital communications equipment for transmission/reception by selecting a transmission/reception common use antenna for the reception system circuit side or the transmission system circuit side.
CONSTITUTION: An FET 11 is connected between an antenna terminal A and a reception system circuit terminal RX, an FET 15 and a resistor R7 are connected in series between the reception system circuit side terminal RX and ground to apply a large level signal reception control signal C3 active when a large level signal is received to a gate of the FET 15. Moreover, a control signal C4 active at the transmission and cleared at the reception of a large level signal is fed to a gate of the FET 12 connected between the reception system circuit side terminal RX and ground. Thus, the FET 11 is inactive at the reception of a large level signal to attenuate a reception signal and the FET 15 is active to terminate the input impedance of the reception system circuit to be a proper value.
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Inventors:
Tetsuya Sekido
Application Number:
JP5381893A
Publication Date:
July 30, 2001
Filing Date:
March 15, 1993
Export Citation:
Assignee:
CASIO COMPUTER CO.,LTD.
International Classes:
H01Q23/00; H01P1/15; H04B1/40; H04B1/44; (IPC1-7): H04B1/44; H01P1/15
Domestic Patent References:
| JP4346513A | ||||
| JP534737U | ||||
| JP5444618U | ||||
| JP479865Y1 |
Attorney, Agent or Firm:
Yoshiyuki Ohsuga