Title:
APPARATUS FOR DETECTING OPERATION OF READING SYSTEM IN EPROM OR EEPROM MEMORY CELL
Document Type and Number:
Japanese Patent JPS6325895
Kind Code:
A
Abstract:
1. A device for detecting the functionning of the read mode in integral circuits of the logic circuit type comprising a nonvolatile memory with the data contained therein, the memory being constituted by a matrix of MOS transistor memory-cells adapted to present defined threshold voltages VT0 and VT1 in accordance with their programming in terms of logic stade "0" or "1", said memory-cells being read out by way of applying a reading voltage VL thereto, such that VT0 < VL < VT1 in normal operation, characterized in that the detection device (A) is constituted by an inverter comprising : - an enhancement MOS-type signal transistor (10) having a threshold voltage VT such that VL < VT < VT1 , and whose gate (14) is connected to the reading voltage, and - a load (11) connected to the reading voltage, the inverter providing a logic signal S used to notify the integrated circuit that the reading voltage exceeds the threshold voltage VT .
Inventors:
YAN GODORONO
Application Number:
JP15526687A
Publication Date:
February 03, 1988
Filing Date:
June 22, 1987
Export Citation:
Assignee:
THOMSON COMPOSANTS MILITAIRES
International Classes:
G11C17/00; G11C5/14; G11C16/06; G11C16/26; (IPC1-7): G11C17/00
Attorney, Agent or Firm:
Yoshio Kawaguchi
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