To satisfactorily perform determination, in spite of variations in the latency value.

A signal to be measured (DUT output signal), from a measuring object device (DUT) 1, is supplied to a first and a second coincidence detection circuits 2, 3. Also, a clock signal supplied to a terminal 4 is supplied to an expected value generating circuit 5, and an expected value of the output value of the device 1 is generated. These expected value data (0) are supplied to the first circuit 2, and the coincidence of the data with the signal to be measured is detected. Furthermore, the taken-out data (0) are supplied to a flip flop 7, and expected value data (1) delayed by one clock are formed. These data (1) are supplied to the second circuit 3, and the coincidence of the data with the signal to be measured is detected. Moreover, coincident signals from the first and second circuits 2, 3 are supplied to an OR (logical sum) circuit 8. This logical sum output signal is extracted to an output terminal 9 as a final coincident signal (determination signal).