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Title:
APPARATUS FOR MEASURING LATCH-UP STRENGTH OF IC
Document Type and Number:
Japanese Patent JPS6466573
Kind Code:
A
Abstract:

PURPOSE: To measure latch-up strength, by providing a pattern generator for holding the logic of a terminal to be tested to a desired state.

CONSTITUTION: The input and output terminals 21, 22 of a latch-up sensor 2 are made conductive by a control signal (a) and predetermined main power supply voltage is generated in a drive power supply 3 by a control signal (a) to drive an IC 1 to be measured. A terminal 12 to be tested is connected to a pattern generator 5 by a control signal (h) and the generator 5 is started by a control signal (e) and stopped when the logic of the terminal 12 attains a predetermined state. Next, a current monitor 6 measures the applied current flowing in the terminal 12 to send out the same to a control part 8 as applied current data (f). The sensor 2 detects the generation of latch-up to send a latch-up generation signal to the control part 8. The control part 8 displays the min. applied current value when latch-up is generated in the IC 1 or performs display to the effect that no latch-up is generated to finish measurement.


Inventors:
TAKAHASHI YUKIHIRO
Application Number:
JP22366487A
Publication Date:
March 13, 1989
Filing Date:
September 07, 1987
Export Citation:
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Assignee:
ANRITSU CORP
International Classes:
G01R31/26; G01R31/28; G01R31/317; H01L27/08; H01L21/66; (IPC1-7): G01R31/26; G01R31/28; H01L21/66; H01L27/08
Attorney, Agent or Firm:
Ryutaro Koike