Title:
ARITHMETIC AMPLIFIER
Document Type and Number:
Japanese Patent JP3478752
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve a through-rate or settling in the step response of an operation amplifier without changing the circuit constitution of the operation amplifier by providing an active element whose resistance value is made variable and a difference controlling means for changing the resistance value of the active element based on the difference of the input of the arithmetic amplifying means.
SOLUTION: This arithmetic amplifier is provided with an active element (nMOS transistor M20) whose resistance value is made variable and a difference controlling means (differential stage of a block 13) for changing the resistance value of the active element based on the difference of the inputs of an arithmetic amplifying means. The difference controlling means detects a differential voltage between the input voltage and output voltage of operation amplifiers 10-12, and converts it into currents, and the currents are transmitted by the current mirror circuits of MOS transistors M13-M18. The transmitted currents are converted into a voltage by using an MOS transistor M19 whose gate and drain are short-circuited as load resistance, and a voltage converted as a value based on a difference between the input voltage and output voltage of the operating amplifier is added to the gate of an nMOS transistor M20.
Inventors:
Takamasa Sakuragi
Application Number:
JP4188499A
Publication Date:
December 15, 2003
Filing Date:
February 19, 1999
Export Citation:
Assignee:
Canon Inc
International Classes:
G06G7/12; H03F3/45; (IPC1-7): H03F3/45; G06G7/12
Domestic Patent References:
| JP927721A | ||||
| JP7221567A | ||||
| JP288318U |
Attorney, Agent or Firm:
Johei Yamashita
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