Title:
演算回路およびその動作制御方法
Document Type and Number:
Japanese Patent JP4272967
Kind Code:
B2
Abstract:
A product-sum operation circuit includes a pulse width/digital conversion circuit ( 9 ) which converts a pulse signal having a pulse width representing an operand value into a digital signal, a sorting circuit ( 4 ) which outputs, in descending or ascending order of magnitude, a plurality of operand values Xi converted into digital signals by the pulse width/digital conversion circuit ( 9 ), and an accumulated sum circuit ( 1 ) which multiplies each operand value output from the sorting circuit ( 4 ) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results. The pulse width/digital conversion circuit ( 9 ) includes a counter ( 10 ) which counts a clock and outputs a count value as a digital signal, and n trailing edge latch circuits ( 11 - 0 - 11 -(n-1)) each of which latches a common count value output from the counter at the trailing edge of the input pulse signal.
Inventors:
Osamu Nomura
Takashi Morie
Teppei Nakano
Takashi Morie
Teppei Nakano
Application Number:
JP2003356627A
Publication Date:
June 03, 2009
Filing Date:
October 16, 2003
Export Citation:
Assignee:
Canon Inc
International Classes:
G06G7/161; G06F17/10; G06N3/063; H03M1/50
Domestic Patent References:
| JP10224220A | ||||
| JP7093277A | ||||
| JP6314347A |
Attorney, Agent or Firm:
Keizo Nishiyama
Yuichi Uchio
Yuichi Uchio