Title:
ARITHMETIC CIRCUIT, ARITHMETIC UNIT AND SEMICONDUCTOR ARITHMETIC CIRCUIT
Document Type and Number:
Japanese Patent JP3226513
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an arithmetic circuit, an arithmetic unit and a semiconductor arithmetic circuit in simple configuration suitable therefor with which the absolute value of a difference and the sum can be operated by high speed analog operation.
SOLUTION: Concerning the arithmetic unit for operating the sum of absolute values of differences between corresponding signals in first signal systems St1 to Stn and second signal systems Si1 to Sin, this unit is provided with plural selector circuits respectively having great input selector circuits 1-1 to 1-n for outputting greater one of two signals and small input selector circuits 2-1 to 2-n for outputting the smaller signal and subtraction circuits 4-1 to 4-n, 5-1 to 5-n, 9-1 to 9-n, 10, 7 and 11 for subtracting the sum of outputs from the small input selector circuits from the sum of outputs from the great input selector circuits.
Inventors:
Naoshi Shibata
Masahiro Honda
Tadahiro Ohmi
Masahiro Honda
Tadahiro Ohmi
Application Number:
JP22559299A
Publication Date:
November 05, 2001
Filing Date:
August 09, 1999
Export Citation:
Assignee:
Semiconductor Science and Engineering Research Center Co., Ltd.
International Classes:
G06G7/12; G06G7/14; G11C11/56; G11C27/00; (IPC1-7): G06G7/14
Domestic Patent References:
| JP2267681A |
Attorney, Agent or Firm:
Takashi Ishida (4 others)
Previous Patent: 放熱機能付きパワー制御器
Next Patent: METHOD FOR CONTROLLING SHAPE OF INCLUSION IN REFINING PROCESS
Next Patent: METHOD FOR CONTROLLING SHAPE OF INCLUSION IN REFINING PROCESS