Title:
演算回路
Document Type and Number:
Japanese Patent JP4073009
Kind Code:
B2
Abstract:
ABSTRACTAn arithmetic circuit to calculate a cumulative value of results of parallel arithmetic processing, in which the increase of the circuit area for multiple-term arithmetic computation and the degradation of accuracy of holding of computation results in a short time can be prevented. The arithmetic circuit has plural analog arithmetic circuits (1) to perform arithmetic processing based on input analog signals, a capacitor (2) to hold a charge amount proportional to a total sum of results of computations by the plural analog arithmetic circuits (1), an A/D conversion circuit (3) to convert the charge amount stored in the capacitor (2) to digital data, and a digital arithmetic circuit (4) to calculate a cumulative value based on the converted digital data.
More Like This:
| JPS62279478 | LOGARITHMIC CONVERSION CIRCUIT |
Inventors:
Keisuke Kesaku
Takashi Morie
Akira Iwata
Osamu Nomura
Takashi Morie
Akira Iwata
Osamu Nomura
Application Number:
JP2002272180A
Publication Date:
April 09, 2008
Filing Date:
September 18, 2002
Export Citation:
Assignee:
Canon Inc
International Classes:
G06J1/00; G06G7/60; G06N3/063
Domestic Patent References:
| JP64003785A | ||||
| JP2000057241A |
Other References:
中村恒博、酒林聰太、森江隆、永田真、岩田穆,任意非線形活性化関数を有するパルス変調方式ニューラルネットワーク回路,電子情報通信学会1999年基礎・境界ソサイエティ大会講演論文集,日本,社団法人電子情報通信学会,1999年 8月16日,SA-1-1,p203-204
森江隆、雨宮好仁、岩田穆,誤差逆伝播学習機能組込み型アナログニューロLSIの回路的検討,電子情報通信学会技術研究報告,日本,社団法人電子情報通信学会,1990年10月25日,Vol.90 No.273,p43-48
森江隆、雨宮好仁、岩田穆,誤差逆伝播学習機能組込み型アナログニューロLSIの回路的検討,電子情報通信学会技術研究報告,日本,社団法人電子情報通信学会,1990年10月25日,Vol.90 No.273,p43-48
Attorney, Agent or Firm:
Yasunori Otsuka
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura