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Title:
ARITHMETIC CODER AND IMAGE PROCESSOR
Document Type and Number:
Japanese Patent JP3929312
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To realize arithmetic encoding and decoding of an ultra-high speed and a high compression ratio regardless of binary data or multi-value data, and also to simplify subsequent operation by making the quantities of arithmetic code uniform in each block.
SOLUTION: An image region judging/layering circuit 12 analyzes an input image, accurately reads its image information and arithmetically encodes it at an ultra-high speed. Disturbance in pipeline involved in generation of normalizing operation can be resolved by employing a future predicting parallel output Qe memory 18. At the time of encoding a multi-value image, a context generator 16 generates a common context without discrimination between AC and DC components in a DCT coefficient. Further, a fixed length source coding circuit 22 is provided to convert an arithmetic code having a variable length code to a code having a fixed length and to output it, thus facilitating editing of a reconstructed image.


Inventors:
Horie, etc.
Application Number:
JP2002002818A
Publication Date:
June 13, 2007
Filing Date:
January 09, 2002
Export Citation:
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Assignee:
Panasonic Communications Co., Ltd.
International Classes:
H04N1/413; H03M7/30; H03M7/40; H04N19/436; H04N19/60; H04N19/625; H04N19/85; H04N19/91; (IPC1-7): H04N1/413; H03M7/30; H03M7/40; H04N7/30
Domestic Patent References:
JP11289461A
JP2001189661A
JP2001086503A
JP11220628A
JP9098294A
JP3001662A
JP7249995A
JP2002033925A
Attorney, Agent or Firm:
Koichi Washida