Title:
演算装置
Document Type and Number:
Japanese Patent JP6773621
Kind Code:
B2
Abstract:
According to an embodiment, an arithmetic device is configured to receive M input signals each representing a two-state value and M coefficients to output an output signal representing a two-state value. The device includes a positive-side current source, a negative-side current source, M cross switches, a coefficient memory unit, and a comparator. The positive-side current source is configured to output a first voltage corresponding to a value of 1/L of the current output from a positive-side terminal. The negative-side current source is configured to output a second voltage corresponding to a value of 1/L of the current output from a negative-side terminal. The memory unit includes M cells corresponding to the respective M coefficients. The comparator is configured to output an output signal having a value corresponding to a comparison result of the first voltage with the second voltage. Each M cell includes a first resistor and a second resistor.
Inventors:
Marugame Takao
Ueda Yoshihiro
Shinji Miyano
Shinichi Yasuda
Yoshifumi Nishi
Matsumoto Mari
Ueda Yoshihiro
Shinji Miyano
Shinichi Yasuda
Yoshifumi Nishi
Matsumoto Mari
Application Number:
JP2017177777A
Publication Date:
October 21, 2020
Filing Date:
September 15, 2017
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06G7/60; G06N3/063
Domestic Patent References:
| JP9198366A | ||||
| JP2000057244A | ||||
| JP4067259A |
Attorney, Agent or Firm:
Sakai International Patent Office