To reduce the total load of a bus line, to increase the working speed, to reduce the power consumption and to improve the reliability of an arithmetic processing system, by placing the 1st, 2nd and 3rd arithmetic parts along three sides of a register file and connecting each arithmetic part to the register file via a data bus.

A 1st data bus 101 connects electrically an arithmetic part 100 to a register file 400, a 2nd data bus 201 connects electrically an arithmetic part 200 to the file 400, and a 3rd data bus 301 connects electrically an arithmetic part 300 to the file 400 respectively. In regard to each register of the file 400, when a selection signal is outputted to a register selection signal line corresponding to a certain register, the value of register cells R10 to R87 of the relevant register are supplied to the parts 100, 200 and 300 via the buses 101, 201 and 301. Then the parts 100 to 300 input the necessary data respectively.