To provide an arithmetic right shift device for calculating a value obtained by operating the n bit arithmetic right shift of m bit negative numbers whose most significant bit is 1 for reducing a circuit scale by reducing a circuit which shift-calculates an absolute value, and for quickening an operation frequency.

This arithmetic right shift device is provided wit: a first latch circuit (124) for inputting and storing m bit negative numbers whose most significant bit is 1; a first complement arithmetic unit (2) for calculating the complement of 1 of the m bit negative numbers stored by the first latch circuit (124); a second latch circuit (101) for inputting and storing m bit shift quantity; a shifter arithmetic unit (4) for operating the logical right shift of the complement of 1 calculated by the first complement arithmetic unit (2) only by the n bit shift quantity stored in the second latch circuit (101); and a second complement arithmetic unit (6) for calculating the complement of 1 of a calculation value logical right shift-operated by the shifter arithmetic unit (4).