Title:
ARITHMETIC UNIT AND METHOD FOR CONTROLLING DELAY TIME
Document Type and Number:
Japanese Patent JP3378440
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To attain an operation with high performance and stability even in the vibration of a delay time due to the vibration of a manufacturing process by providing an end detecting circuit which detects the end of the arithmetic operation of an arithmetic circuit, and a synchronizing clock generating circuit which generates a clock synchronizing with an arithmetic end signal.
SOLUTION: This device is provided with two termination detecting circuits 107 and 108 which detect the termination of the arithmetic operation of arithmetic circuit 101 and 104, synthesizer 109 which inputs a detected arithmetic termination signal, and detects the termination of the arithmetic operation of all the arithmetic circuits, and synchronizing clock generating circuit 110 which generates a clock synchronizing with the arithmetic termination signal detected by this synthesizer 109. Then, the operation is attained by using this generated clock. Therefore, the operation is not decided by a clock applied from the outside, and performance is decided by the slowest arithmetic circuit among the plural arithmetic circuits. Thus, the operation with high performance and stability can be obtained against the variation of a delay time due to the variation of a manufacturing process.
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Inventors:
Seigo Suzuki
Shinichi Yoshioka
Shinichi Yoshioka
Application Number:
JP19242796A
Publication Date:
February 17, 2003
Filing Date:
July 22, 1996
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F7/00; G06F1/08; G06F9/38; G06F11/24; H03L7/00; G06F11/30; G06F11/34; (IPC1-7): G06F7/00
Domestic Patent References:
| JP6152386A | ||||
| JP4270414A | ||||
| JP60218134A | ||||
| JP4982244A | ||||
| JP52128030A |
Attorney, Agent or Firm:
Hidekazu Miyoshi (3 outside)