To improve the arithmetical ability by effectively utilizing a pipeline by decreasing stall by letting plural instruction trains having no dependent relation alternately flow to the pipeline at a pipeline type arithmetic unit.

This arithmetic unit is provided with two pairs (or more pairs of) instruction memory data storage means 3 and 3a, data memory address storage means 5 and 5a, storage means 8 and 8a for 1st instruction decoder 4, data memory data storage means 7 and 7a, storage means 10 and 10a for 2nd instruction decoder 9, and storage means 12 and 12a for the arithmetic result. When alternately performing arithmetic at an arithmetic part 11 while dividing modulating processing, demodulating processing, synchronizing processing, voice encoding processing and voice decoding processing in the field of communication, the respective storage means are allocated to respective operations. Since the dependent relation is reduced in respective middle operations, the respective operations can be alternately executed.