PURPOSE: To perform various shift processings efficiently and reduce the amount of hardware to facilitate an arithmetic unit into an LSI by cascading a right shift circuit and a left shift circuit with an arithmetic operating circuit between them.
CONSTITUTION: A right shift circuit 27 shifts right output data from a mantissa part selecting part 24 by a prescribed number of bits on a basis of shift extent data from a selector 36 and gives shifted data to an arithmetic operating circuit 28. Output data of the circuit 27 and that of the selecting part 24 are inputted to the circuit 28 and are subjected to arithmetic operation, and the circuit 28 gives the operation result to a temporary register 29. A left shift circuit 33 shifts left output data of the register 29 by a prescribed number of bits on a basis of shift extent data from a selector 37 and gives shifted data to an output register 35. The circuit 27, the circuit 28, and the circuit 33 are operated to perform arithmetic shift, addition/subtraction of the mantissa part, and normalizing shift respectively, thus performing various shift processings efficiently.
MOGI HISATOSHI
MORI GIICHI
NOMURA AKIRA
| JPS5776634A | 1982-05-13 | |||
| JPS595344A | 1984-01-12 |