PURPOSE: To make effective arrangement work and improve arrangement quality by performing delay calculation for each wiring and correcting an arrangement position based upon the result of the delay calculation.

CONSTITUTION: Pairs of functional blocks B1 and B1', B2 and B2', and B3 and B3' are the same functional blocks but are different in their configurations. After among several combinations of temporal layout examples in such manner, a temporal layout being a minimum in the average of wiring lengths is selected, the delay calculation is performed. For the delay calculation, the existence of a flip-flop at the center of gravity of the blocks is assumed (the center of gravity is indicated by a mark X in the figure), and the center of gravity is taken as one end, and further the sum of the lengths of lines being perpendicular to each other is calculated, and finally a delay value corresponding to the sum is calculated. In such a manner, with an optimum layout taking the delay value into consideration, quality in an LSI design is improved and further preparation of the functional block and temporal layout of the functional block are automatically achieved. Hereby, effectiveness of the work is realized.