PURPOSE: To provide arrangement in which an additional address space larger than the valid address space of a processor is created.
CONSTITUTION: Known arrangement for connecting a processor 1 with a memory 3 creates an additional address space larger than the valid address space of the processor 1, and operates address adjustment for addressing by loading data generated from the processor 1 as a start address signal from a memory 3 is response to a first address. Here, many registers are used, and this arrangement is complicate, and as a result, it is slow and expensive. In this simple, and as a result, fast and inexpensive arrangement 2, another address signal is generated for the memory in response to a second address of the processor 1, and this another address signal is the function of the second address number generated with the start address signal.
| WO/2021/070016 | VIRTUAL MEMORY METADATA MANAGEMENT |
| JP2009259103 | BOOT SYSTEM |
| WO/2001/061472 | INCREMENTAL CLASS UNLOADING IN A TRAIN-ALGORITHM-BASED GARBAGE COLLECTOR |
ROBU PIITAASU
MAACHIN KURAASU DE RANGE
| JPS62226345A | 1987-10-05 | |||
| JPS61131137A | 1986-06-18 | |||
| JPH0319063A | 1991-01-28 |