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Patent Searching and Data


Title:
ARTIFICIAL TROUBLE GENERATING DEVICE
Document Type and Number:
Japanese Patent JPS61240335
Kind Code:
A
Abstract:

PURPOSE: To perform a test owing to the generation of an artificial trouble with no matching of the generating timing of the artificial trouble, by securing such a constitution where the artificial trouble of a main memory is not produced with accesses excepting for those given from a device to be tested.

CONSTITUTION: A central processing unit 10 sets the data on the diagnosis instructions to a diagnosis register RG31 and a mask RG32 of an artificial trouble generating device 1 via a diagnosis processor 20. If the trouble data reporting an address parity error is set to the register RG31, only an output line 114 of the RG31 is set at level '1'. While the encoding value which produces a trouble is set to the mask RG32 if an access request is given from a channel CH device 60. The access request given from the device 60 is supplied to a comparator 34 via an RG35. The comparator 34 compares the decoded 33 signal of the RG32 with the signal given from the RG35. Then the signal '1' is delivered when the coincidence is obtained between both signals, and the error report of level '1' is transmitted to the unit 10 and CH devices 60W66 via an AND gate 38, an error RG54 and an OR gate 51 and through a signal line 110.


Inventors:
NISHIMOTO KUNIO
Application Number:
JP8154885A
Publication Date:
October 25, 1986
Filing Date:
April 17, 1985
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/22; G01R31/319; (IPC1-7): G06F11/22
Attorney, Agent or Firm:
Uchihara Shin