Title:
ASSOCIATIVE MEMORY
Document Type and Number:
Japanese Patent JPS648471
Kind Code:
A
Abstract:
PURPOSE:To omit the logical inversion of a bit line and an inversed bit line at the time of writing and comparing data by connecting a bit line and an inverted bit line to the gates of two writing transistors (TRs) in an associative memory. CONSTITUTION:A memory cell is constituted of p-channel TRs (PTRs) 1, 2 and n-channel TRs 3-6, 9, 14. At the time of writing data, a control line 22 is turned to a high potential, data to be written are applied to a data input 26 and then a word line 12 is turned to a high potential. At that time, data are written so that the PTR 2 or PTR 1 is turned on in accordance with the state that a bit line 10 or an inverted bit line 11 is in the high potential. On the other hand, case of comparing data, a work line 12 and the control line 22 are successively turned to a low potential and a coincidence line 13 is precharged. When the control line 22 is turned to the high potential and the same signal as that written in the bit line 10 and the inverted bit line 11 is applied, a compared result is obtained on the coincidence signal 13.
Inventors:
NAKAMURA KAZUO
ENAMI YUKIKO
ENAMI YUKIKO
Application Number:
JP16433587A
Publication Date:
January 12, 1989
Filing Date:
June 30, 1987
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L27/11; G06F15/00; G06F15/04; G11C15/04; H01L21/8244; H01L27/10; (IPC1-7): G06F15/00; G06F15/04; H01L27/10
Attorney, Agent or Firm:
Masuo Oiwa
Next Patent: WATER RESISTING PACK FOR QUALITY RETAINING AGENT