Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
AUTOMATIC CIRCUIT LAYOUT DECIDING METHOD
Document Type and Number:
Japanese Patent JPS648481
Kind Code:
A
Abstract:

PURPOSE: To increase the transistor density to minimize array dimension by keeping minimum the congestion of useable routing path by speedily and exactly deciding all the mutual connections required for an integrated circuit like a gate array.

CONSTITUTION: The average position of terminals on a grid is found, and a closest 1st terminal and a 2nd terminal closet to the 1st terminal are found along the path of (x) or (y) on the grid. Next, a 1st path is established between the 1st and 2nd terminals and when that path is one line, it is set as the routing path. Continuously, a path is established by finding the side of established path having not set side or a terminal closest to an apex and when any apex or terminal common for the side set to that path is not contained, it is set as a routing path. Such a procedure is executed while using a computer 100, the congestion of the usable routing path is kept minimum and the effective layout of paths is made possible.


Inventors:
JIYON JIYOSEFU DOIRU JIYUNIA
Application Number:
JP6016688A
Publication Date:
January 12, 1989
Filing Date:
March 14, 1988
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
ETA SYSTEMS INC
International Classes:
G06F17/50; (IPC1-7): G06F15/60
Attorney, Agent or Firm:
Akira Asamura (2 outside)