Title:
AUTOMATIC DESIGNING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH05335417
Kind Code:
A
Abstract:
PURPOSE: To reduce the dead space of an internal circuit and a peripheral circuit to a minimum, and arrange chip terminals at optimum positions, without deteriorating LSI chip function, by using an automatic layout program.
CONSTITUTION: As to a block to be registered in a library for automatic layout, a peripheral circuit 1 or the like is registered as the circuit block, so as to be different from the terminal block constituted of lines, terminals 4, etc. Thereby useless space is eliminated from the arrangement on a chip.
Inventors:
AKUTAGAWA MASANAO
Application Number:
JP16372592A
Publication Date:
December 17, 1993
Filing Date:
May 30, 1992
Export Citation:
Assignee:
TOSHIBA CORP
TOSHIBA MICRO ELECTRONICS
TOSHIBA MICRO ELECTRONICS
International Classes:
H01L21/82; H01L21/822; H01L27/04; (IPC1-7): H01L21/82; H01L27/04
Attorney, Agent or Firm:
Toshi Takemura