PURPOSE: To generate a circuit by a small number of connecting lines or the smallest number of connecting lines by settling such a problem as a redundant connecting line is generated between a register and a bus, when an automatic register allocation is executed, and a circuit generated as a result of synthesis of a high level becomes large, with regard to a register allocation process in an automatic design process of a hardware circuit called the high level synthesis.
CONSTITUTION: The device is provided with a means 105 for calculating variable link information for showing to which bus each variable is to be connected from an operation executing schedule, a means 106 for storing the variable link information, and a register allocating means 107 for allocating the connecting line between a register and a bus so as not to be increased if possible from the stored variable link information and a register allocation state, at the time of allocating the variable to each register by utilizing the left edge algorithm based on a life time being a period in which variable is used.
MATO RYUICHI
ARAKI HITOSHI
NOJIMA SHINJI
