PURPOSE: To allow the system to cope with the change in a preamble signal length by providing a frequency divider circuit selecting independently and optionally a BSS time slot time width and its time slot generation timing interval.

CONSTITUTION: When an output terminal QB' of the 2nd frequency divider circuit 20 is at L level at first, an NAND gate 33 goes to H level, FF11∼14 of the 1st frequency divider circuit 10 are reset and an H level is outputted to an output terminal QB. When the terminal QB' changes to H level, the gate 33 goes to an L level and the FF11∼14 are cleared. When a clock pulse is inputted to an input terminal CK1 of the circuit 10 succeedingly, the level of the terminal QB is changed to an L level soon and the gate 33 is brought back to the H level again. The time slot generation interval TD and the time width TW of the BSS time slot are changed optionally by selecting properly the values of frequency division numbers n, m and the frequency of pulses CK1, CK2.