To provide a bi-polar multiplying circuit with linearity and a wide input voltage range.

Bi-polar transistors Q1, Q2, Q3, and Q4 whose emitters are connected and bi-polar transistors Q5, Q6, Q7, and Q8 whose emitters are connected form first and second differential amplifier circuits 1 and 2. The collectors of the transistors of the differential amplifier circuits 1 and 2 are cross-linked so that a multiplier core circuit can be constituted. A first input voltage Vx is respectively impressed between the bases of the transistors Q1 and Q2 and between the bases of the transistors Q5 and Q6. A Yx/2 is respectively impressed between the bases of the transistors Q3 and Q4 and between the bases of the transistors Q7 and Q8. A third differential amplifier circuit 3 constituting a driving circuit has the same constitution as the first and second differential amplifier circuits 1 and 2 while a second input voltage Vy is impressed instead of the first input voltage Vx.