Title:
記憶装置のバイアス印加方法、および記憶装置
Document Type and Number:
Japanese Patent JP4421615
Kind Code:
B2
Abstract:
In Step 1, a bias is applied (ON) to all of vertical rows Z1(0) to Z1(2). With respect to the horizontal rows, a bias is not applied (OFF) to a horizontal row Z2(0) where the defective sector exists and a bias is applied (ON) to the other horizontal rows Z2(1) and Z2(2). On the sectors in the horizontal rows Z2(1) and Z2(2), a voltage stress is applied and an access operation is performed. In Step 2, with respect to the vertical rows, a bias is not applied (OFF) to a vertical row Z1(1) where the defective sector exists and a bias is applied (ON) to the other vertical rows Z1(0) and Z1(2). With respect to the horizontal rows, a bias is applied (ON) to the horizontal row Z2(0) where the defective sector exists, and no bias is applied (OFF) to the other horizontal rows Z2(1) and Z2(2). By the two steps, a voltage stress can be applied once to the sectors other than the defective sector.
Inventors:
Kenta Kato
Takaaki Furuyama
Takaaki Furuyama
Application Number:
JP2006548652A
Publication Date:
February 24, 2010
Filing Date:
December 24, 2004
Export Citation:
Assignee:
Spansion LLC
International Classes:
G11C29/04; G11C16/02; G11C16/04; G11C16/06; G11C29/06; G11C29/34
Domestic Patent References:
| JP2000137991A | ||||
| JP2001084800A | ||||
| JP2001101899A | ||||
| JP9288899A | ||||
| JP8106796A | ||||
| JP2000040395A | ||||
| JP2004253021A |
Attorney, Agent or Firm:
Hiroto Tanaka
Ikuo Yamanaka
Ikuo Yamanaka