To provide a bias circuit for uniformly suppressing bias currents even when the threshold voltage of a transistor fluctuates.

A resistance element R1 whose resistance value fluctuates while being linked with the threshold of a transistor FET1 is connected between a gate bias supply terminal T3 and a gate terminal G. Even when the threshold of the transistor FET1 fluctuates, the resistance value is increased/decreased according to the increase/decrease of the threshold. When the threshold is increased, the resistance value is decreased, and a bias voltage is adjusted so as to be increased according to a resistance partial pressure. When the threshold is decreased, the resistance value is increased, and the bias voltage is adjusted so as to be decreased according to the resistance partial pressure. The transistor FET1 is constituted as a junction transistor having a first conductive channel and a second conductive gate, and a resistance element R1 is manufactured by a second conductive type semiconductor area.