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Patent Searching and Data


Title:
BIAS CIRCUIT
Document Type and Number:
Japanese Patent JPH0983269
Kind Code:
A
Abstract:

To attain a stable operation of the circuit and to reduce the circuit scale even when multi-stage connection of a TR circuit and a composite circuit are configured by providing a bias means and an input frequency selection means to the bias circuit deciding the operating point of TRs.

The bias circuit provides a bias current to a base and a collector of a TR 1 to decide the operating point of the TR 1 and a frequency selection means is provided to the base. The frequency selection means is made up of a resonance circuit 13 consisting of a resistor 10, a distributed constant line 11 and a capacitor 12 and passes a signal within a prescribed band and attenuates the frequency signal at the outside of the prescribed band. Thus, in the case of connecting amplifier circuits in multi-stage or configuring a composite circuit having amplifier circuits and a mixer circuit inbetween, they are stably operated without having an effect the noise characteristic and the bias circuit is realized with a small scale without addition of a complicated circuit.


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Inventors:
IWATSUKI HAJIME
SUGAWARA HIDEO
Application Number:
JP24190395A
Publication Date:
March 28, 1997
Filing Date:
September 20, 1995
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03F3/60; H03F1/34; H03F1/56; H03F3/191; (IPC1-7): H03F3/60; H03F1/34
Attorney, Agent or Firm:
Takashi Ishida (3 others)