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Patent Searching and Data


Title:
BINARY SIGNAL TRANSFER CIRCUIT
Document Type and Number:
Japanese Patent JPH07273748
Kind Code:
A
Abstract:

PURPOSE: To reduce the power consumption by supplying a specific signal out of a binary signal to a simultaneous bidirectional binary signal transfer circuit at the time when an input signal is ineffective.

CONSTITUTION: When the input signal supplied to an input terminal 8 is ineffective, the output of an AND circuit 2 goes to the low level independently of the value of the input signal, and this value is held in an FF circuit 3. The output of the circuit 3 is inputted to a simultaneous bidirectional binary signal transfer circuit 1 and is outputted to an output terminal 13 through an FF circuit 7 on the other party side. When the input signal supplied to an input terminal 11 is ineffective, the low level is inputted to the circuit 11 through an AND circuit 5 and an FF circuit 6 and is outputted to an output terminal 10 through an FF circuit 4 in the same manner. Consequently, if input signals supplied to terminals 8 and 11 are ineffective together, signals inputted to the circuit 1 go to the low level together, and a through current doesn't flow to a transfer line 16, and the power consumption is reduced.


Inventors:
SUZUKI EIJI
ISHIKAWA HISASHI
Application Number:
JP6038494A
Publication Date:
October 20, 1995
Filing Date:
March 30, 1994
Export Citation:
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Assignee:
KOFU NIPPON DENKI KK
International Classes:
H03K17/00; H03K17/16; H03K19/0175; H04L5/14; G01R31/28; (IPC1-7): H04L5/14; G01R31/28; H03K17/00; H03K17/16; H03K19/0175
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)