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Patent Searching and Data


Title:
BIPOLAR MULTIPLYING CIRCUIT AND VOLTAGE ADDING CIRCUIT USED FOR SAME
Document Type and Number:
Japanese Patent JPH11316793
Kind Code:
A
Abstract:

To provide a voltage adding circuit which has high input impedance and can be actualized with small chip area.

Emitter-coupled bipolar transistors Q1a and Q2a, and Q3a and Q4a form 1st and 2nd unbalanced differential couples respectively. The 1st and 2nd unbalanced differential couples are driven by constant-current sources 1a and 2a respectively. A 1st input voltage V1 is differentially inputted between the bases of the bipolar transistors Q1a and Q2a and a 2nd input voltage V2 is inputted to the base of the bipolar transistor Q3a. The 1st and 2nd unbalanced differential couples generate a 1st and a 2nd offset voltage. The collector currents of the bipolar transistors Q4a and Q1a are equal to each other. An output voltage including the sum of the sum of the 1st and 2nd input voltages V1 and V2 and the sum of the 1st and the 2nd offset voltage is developed at the base of the diode-connected bipolar transistor Q4a.


Inventors:
KIMURA KATSUHARU
Application Number:
JP12152898A
Publication Date:
November 16, 1999
Filing Date:
April 30, 1998
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06G7/163; H03F3/45; H03G11/08; (IPC1-7): G06G7/163; H03F3/45; H03G11/08
Attorney, Agent or Firm:
Izumi Katsufumi