Title:
BIT ERROR RATIO MEASURING DEVICE FOR DIGITAL COMMUNICATION SYSTEM
Document Type and Number:
Japanese Patent JP2751673
Kind Code:
B2
Abstract:
PURPOSE: To speedily measure a bit error ratio by eliminating time for newly fetching a pseudo random pattern in a case out of synchronization at a digital communication system.
CONSTITUTION: Pseudo random pattern data inputted through a system to be measured are read by first and second pattern generators 30 and 32 for comparison. A first changeover SW 30a is connected to the side of a contact A, and a second changeover SW 32a is connected to the side of a contact C. A system changeover SW 34 is connected to the side of a contact E and inputted to an EX-OR gate 16 for comparison, and the data are compared. When synchronism is obtained, the first changeover SW 30a is switched to the side of a contact B and the bit error ratio is measured. In the case out of synchronism, the first changeover SW 30a is switched to the side of the contact A, the system changeover SW 34 is switched to the side of a contact F, and synchronism is obtained again by using the pseudo pattern data read in the second pattern generator 32 for comparison.
Inventors:
KIZU MASAFUMI
Application Number:
JP18678691A
Publication Date:
May 18, 1998
Filing Date:
July 26, 1991
Export Citation:
Assignee:
TOYOTA JIDOSHA KK
International Classes:
H04L1/00; (IPC1-7): H04L1/00
Domestic Patent References:
| JP6081933A |
Attorney, Agent or Firm:
Kenji Yoshida (2 outside)