Title:
ビットオーダバイナリ加重乗算器／積算器
Document Type and Number:
Japanese Patent JP7384925
Kind Code:
B2
Abstract:
Various arrangements for performing vector-matrix multiplication are provided here. Digital input vectors that include binary-encoded values can be converted into a plurality of analog signals using a plurality of one-bit digital to analog converters (DACs). Using an analog vector matrix multiplier, a vector-matrix multiplication operation can be performed using a weighting matrix for each bit-order of the plurality of analog signals. For each performed vector-matrix multiplication operation, a bit-ordered indication of an output of the analog vector matrix multiplier may be stored. A bit-order weighted summation of the sequentially performed vector-matrix multiplication operation may be performed.
Inventors:
Yen, She-Fa
Guo, Frank Zen-Wen
Guo, Frank Zen-Wen
Application Number:
JP2021565733A
Publication Date:
November 21, 2023
Filing Date:
April 22, 2020
Export Citation:
Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
G06F17/16; G06G7/16; G06G7/184
Domestic Patent References:
| JP2018501536A | ||||
| JP4177529A | ||||
| JP10078994A | ||||
| JP2002049884A |
Foreign References:
| US20190102358 | ||||
| US20050125477 |
Attorney, Agent or Firm:
Sonoda & Kobayashi Patent Attorneys Corporation
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