To provide a step-up circuit of high efficiency which reduces substrate bias effect and can avoid voltage loss in raised voltage by a pn forward bias in a triple well structure.

A plurality of stages of pump cells having first n-type MOSFETs 10 to 12 and step-up capacitors C2, C4 and C6 driven by a clock signal connected to a source-side of first n-type MOSFET are installed by connecting a source of first n-type MOSFET to a drain of first n-type MOSFET in the next stage. First n-type MOSFETs 11 and 12 in the pump cells in the second and subsequent stages are n-type MOSFET of the triple well structure. N wells are individually connected to the drains, and p wells are connected to the drains of first n-type MOSFETs 10 and 11 in the prestage through second n-type MOSFETs 14 and 15 where gates and the drains are connected.

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