PURPOSE: To shorten an execution time by performing efficient pipeline processing when a program including a branch instruction based upon conditions is executed.

CONSTITUTION: A branch destination instruction code is stored in a branch destination table 6 corresponding to the instruction address of the branch instruction. An instruction code 2A read out of a program memory 2 with an instruction address 1A generated by a program sequencer 1 is temporarily stored in a 2nd instruction register 14 and the branch destination instruction code read out of the branch destination table 6 is temporarily stored in a 1st instruction register 13. A selector 15 selects one of the outputs of the instruction registers 13 and 14 and supplies it to an instruction decoder 4. Consequently, the need for a read phase for reading the branch destination instruction out of the program memory 2 is eliminated and the pipeline processing can be executed without any deviation in timing.