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Title:
BREAK POINT CONTROLLING SYSTEM
Document Type and Number:
Japanese Patent JPS5469348
Kind Code:
A
Abstract:

PURPOSE: To make easy adjustment, maintenance and inspection of a data processor including program deback by making possible free decision of the break point of a program to be executed.

CONSTITUTION: The control circuit is constituted by BP number detection circuit 1 which detects the device number of break point BP sent from the data processor to address by line ADR, first comparator 3, register number detection circuit 5 which applies entered signal RR to register 4 where the number of execution of a circular program is set through SATA, counter 6 which counts the number of BP passage, and second comparator 7 which compares the output of register 4 with that of counter 6 on occasion and, when the output coincides with the other one, applies interrupt signal INT for stop of program execution.


Inventors:
MIYAZAKI MASAMITSU
OOTA YOSHIHITO
Application Number:
JP13623677A
Publication Date:
June 04, 1979
Filing Date:
November 15, 1977
Export Citation:
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Assignee:
HITACHI ELECTRONICS
International Classes:
G06F11/28; (IPC1-7): G06F9/18
Domestic Patent References:
JPS4735832B1
JPS506747U1975-01-23
JPS5319738A1978-02-23



 
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