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Title:
BUFFER CONTROLLING SYSTEM
Document Type and Number:
Japanese Patent JPS60559
Kind Code:
A
Abstract:

PURPOSE: To speed up data transfer by making checking of destination address included in the data to be transferred to a buffer simultaneously with data transfer.

CONSTITUTION: Data that passed an interface section 3 are transferred to a buffer 1 without waiting the result of judgement of an address checking section 5. Instead of it, everytime when one frame is received, a buffer controlling section 4 saves the value of an address counter 6 at that time to an address restoring register 7. The address checking section 5 sends only address error ERR to the controlling section 4. Accordingly, the value of the register 7 is renewed by the value of the counter 6 so far as the address of each frame is oneself. However, if address error ERR occurs, the control section 4 stops data transfer, and at the same time, returns the value of the register 7 to the counter 6, and clears data of relevant buffer address. Thus, address check and data transfer are carried out simultaneously.


Inventors:
KAMIDATE MORIHIRO
YAMAMOTO NOBORU
Application Number:
JP10864783A
Publication Date:
January 05, 1985
Filing Date:
June 17, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F13/38; G06F13/42; (IPC1-7): G06F13/38
Attorney, Agent or Firm:
Minoru Aoyagi



 
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