PURPOSE: To decreases the deciding frequency and to ensure the smooth input/ output of data by deciding the flags for each transfer of a prescribed block via a circuit set at the reception side.

CONSTITUTION: The data divided into blocks are written (DI1WDIM) into and read (DO1WDOM) output of a memory 1 for each prescribed number of data words. Then the write clocks SI and the read clocks SO are supplied to a 1st shift register 2 every data word and a write request flag, the inverse of IR is delivered from a stage set at the other side of the register 2. While the write clocks BSI and read clocks BSO are supplied to a 2nd shift register 3 and a read request flag, the inverse of OR is delivered from a stage of one of both sides of the register 3 every block for transfer of blocks. Thus a circuit set at the reception side is just required to judge the flag at every transfer of a prescribed block. As a result, the deciding frequency is decreased and the smooth input/output of data are secured.